CTL130PS10-T52

Features 

• Drain-Source Breakdown Voltage VDSS-100V

• Drain-Source On-Resistance 

RDS(ON) 160mΩ, at VGS= -10V, ID= -3.6A 

RDS(ON) 170mΩ, at VGS= -4.5V, ID= -3.4A

• Continuous Drain Current at TC=25℃ ID =-11A

• Advanced high cell density Trench Technology 

• RoHS Compliance & Halogen Free 

Applications 

• Power Management in Note book 

• DC/DC Converter 

• Load Switch

Description 

The CTL130PS10-T52 is the P-Channel logic 

enhancement mode power field effect transistors 

are produced using high cell density, DMOS trench 

technology. This high density process is especially

tailored to minimize on-state resistance. These 

devices are particularly suited for low voltage 

application such as cellular phone and notebook 

computer power management and other battery 

powered circuits , and low in-line power loss are 

needed in a very small outline surface mount 

package.