GDP1BFLM-CA

FEATURES

◆ Power supply: VDD = VDDQ = 1.35V (1.283V - 1.45V)

◆ Backward compatible to VDD = VDDQ = 1.5V ± 0.075V 

- Supports DDR3L devices to be backward compatible in 1.5V application

◆ Package: 96-Ball FBGA (x16)

◆ Array configuration: 8 Banks

◆ 8n-Bit prefetch architecture

◆ Differential clock inputs (CK, CK#)

◆ Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals

◆ Programmable CAS (READ) latency (CL)

◆ Programmable posted CAS additive latency (AL)

◆ Programmable CAS (WRITE) latency (CWL)

◆ Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])

◆ Selectable BC4 or BL8 on-the-fly (OTF)

◆ Self refresh mode

◆ Operating case temperature: -40℃ ≤ TCASE ≤ 95℃

◆ Average refresh period:

-7.8us at 0℃ ≤ TCASE ≤ 85℃

-3.9us at 85℃＜TCASE ≤ 95℃

◆ JEDEC JESD79-3F compliant

◆ RoHS compliant

Note:

1. The functionality described and the timing specifications included in this data sheet are for the DLL enabled mode of 

operation.