GD5F2GQ5UE

FEATURE

◆ 2Gb SLC NAND Flash ◆ Advanced security Features

- 8K-Byte OTP Region

◆ Page Size 

- Internal ECC On (ECC_EN=1, default): ◆ Program/Erase/Read Speed 

Page Size：2048-Byte+64-Byte - Page Program time: 300us typical

- Internal ECC Off (ECC_EN=0): - Block Erase time: 3ms typical

Page Size：2048-Byte+128-Byte - Page read time: 60us maximum

◆ Standard, Dual, Quad SPI,DTR ◆ Low Power Consumption

- Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD# - 30mA maximum active current

- Dual SPI: SCLK, CS#, SIO0, SIO1, WP#, HOLD# - 50uA maximum standby current

- Quad SPI: SCLK, CS#, SIO0, SIO1, SIO2, SIO3

- DTR(Double Transfer Rate) Read : SCLK, CS#, SIO0, ◆ Enhanced access performance

SIO1, SIO2, SIO3, DQS - 2Kbyte cache for fast random read

- Cache read and cache program

◆ High Speed Clock Frequency

- 3.3V: 104MHz for fast read with 30pF load ◆ Advanced Feature for NAND

- 1.8V: 80MHz for fast read with 30pF load - Factory good block0

- 3.3V: Quad I/O Data transfer up to 416Mbits/s

- 1.8V: Quad I/O Data transfer up to 320Mbits/s ◆ Reliability- Factory good block0

- P/E cycles with ECC: 100K

◆ Software/Hardware Write Protection - Data retention: 10 Years

- Write protect all/portion of memory via software

- Register protection with WP# Pin ◆ Internal ECC

- 4bits /528Byte

◆ Single Power Supply Voltage

- Full voltage range for 1.8V: 1.7V ~ 2.0V

- Full voltage range for 3.3V: 2.7V ~ 3.6V

Note: (1) ECC is on default, which can be disable by user.

GENERAL DESCRIPTION 

SPI (Serial Peripheral Interface) NAND Flash provides an ultra-cost effective while high density non-volatile memory 

storage solution for embedded systems, based on an industry-standard NAND Flash memory core. It is an attractive

alternative to SPI-NOR and standard parallel NAND Flash, with advanced features.

• Total pin count is 8, including VCC and GND

• Density 2Gb

• Superior write performance and cost per bit over SPI-NOR

• Significant low cost than parallel NAND

This low-pin-count NAND Flash memory follows the industry-standard serial peripheral interface, and always remains the 

same pin out from one density to another. The command sets resemble common SPI-NOR command sets, modified to 

handle NAND specific functions and added new features. GigaDevice SPI NAND is an easy-to-integrate NAND Flash 

memory, with specified designed features to ease host management:

• User-selectable internal ECC. ECC parity is generated internally during a page program operation. When a page 

is read to the cache register, the ECC parity is detected and corrects the errors when necessary. The device outputs 

corrected data and returns an ECC error status.

• Internal data move or copy back with internal ECC. The device can be easily refreshed and manage garbage

collection task, without need of shift in and out of data. This command string can only be used on blocks with the 

same parity attribute.

• Power on Read with internal ECC. The device will automatically read first page of fist block to cache after power 

on, then host can directly read data from cache for easy boot. Also the data is promised correct by internal ECC when 

ECC enabled.

It is programmed and read in page-based operations, and erased in block-based operations. Data is transferred to or from 

the NAND Flash memory array, page by page, to a data register and a cache register. The cache register is closest to I/O 

control circuits and acts as a data buffer for the I/O data; the data register is closest to the memory array and acts as a 

data buffer for the NAND Flash memory array operation. The cache register functions as the buffer memory to enable page 

and random data READ/WRITE and copy back operations. These devices also use a SPI status register that reports the 

status of device operation.