GDQ2A8AA-WJ

FEATURES

◆ Power supply: VDD = VDDQ = 1.2V (1.14V to 1.26V); VPP = 2.5V (2.375V to 2.75V)

◆ JEDEC standard package: 78-Ball FBGA (x8)

◆ Array Configuration: 16 Banks (x8) 4 groups of 4 banks

◆ 8n-Bit prefetch architecture

◆ Burst Length (BL): 8 and 4 with Burst Chop (BC)

◆ Programmable CAS Latency (CL)

◆ Programmable CAS Write Latency (CWL)

◆ Internal generated VREF for data inputs

◆ Data Mask (DM) for write data

◆ On-Die Termination (ODT): Support Nominal, Park and Dynamic ODT

◆ Interface: 1.2V Pseudo Open Drain (POD) IO

◆ Differential clock and data strobe inputs (CK_t ,CK_c; DQS_t, DQS_c)

◆ Per DRAM Addressability (PDA)

◆ Data Bus Inversion (DBI)

◆ Asynchronous reset for power up

◆ Maximum Power Saving Mode (MPSM)

◆ Precharge: Auto precharge option for each burst access

◆ Operating case temperature: -40°C ≤ TCASE ≤ 95°C

◆ Support auto-refresh and self-refresh mode

◆ Average Refresh Period: 

-7.8μs at -40°C ≤ TCASE ≤ 85°C

-3.9μs at 85°C < TCASE ≤ 95°C

◆ Fine granularity refresh 2x, 4x mode for smaller tRFC

◆ Programmable data strobe preambles

◆ Command Address (CA) Parity is supported

◆ Write Cyclic Redundancy Code (CRC) is supported

◆ Connectivity test mode (TEN) is supported

◆ Gear Down Mode

◆ Output driver calibration through ZQ pin (RZQ: 240ohm ± 1%)

◆ JEDEC JESD-79-4D compliant

◆ RoHS compliant

Note:

1. The functionality described and the timing specifications included in this datasheet are for the DLL Enabled mode of 

operation (normal operation), unless specifically stated otherwise.