U74HCT165

DESCRIPTION 

The U74HCT165 is an 8-bit parallel-load shift register that, 

when clocked, shifts the data toward a serial (QH) output. 

Parallel-in access to each stage is provided by eight individual 

direct data (A-H) inputs these are enabled by a low level at 

shift/load (SH/ LD ) input. The U74HCT165 also features a 

clock-inhibit (CLK INH) function and a complementary serial ( QH ) 

output. 

Clocking is accomplished by a low-to-high transition of the 

clock (CLK) input while SH/ LD is held high and CLK INH is held 

low. The functions of CLK and CLK INH are interchangeable. 

Since a low CLK and a low-to-high transition of CLK INH also 

accomplish clocking, CLK INH should be changed to the high 

level only while CLK is high. Parallel loading is inhibited when 

SH/ LD is held high. While SH/ LD is low, the parallel inputs to 

the register are enabled independently of the levels of the CLK, 

CLK INH, or serial (SER) inputs. 

The inputs are compatible with TTL, NMOS and CMOS output 

voltage levels. 

FEATURES 

* Complementary Outputs 

* Direct Overriding Load (Data) Inputs 

* Gated Clock Inputs 

* Parallel-to-Serial Data Conversion 

* Compatible with TTL, NMOS, CMOS output voltage levels

规格书U74HCT165