U74LVC563

DESCRIPTION 

The U74LVC563 is a octal transparent D-TYPE latches with 3-state 

outputs. When the latch-enable (LE) is high, the Q outputs follow the 

complements of the D inputs. When LE is low, the Q outputs are latched 

at the inverses of the levels set up at the D inputs. 

When the output-enable ( OE ) input is high, the Q outputs are in a 

high-impedance state, and the outputs neither load nor drive the bus lines. 

The high-impedance state and increased drive provide the capability to 

drive bus lines without interface or pull-up components. While the outputs 

are in the high-impedance state, old data can be retained or new data can 

be entered, i.e. OE does not affect the internal operations of the latches. 

When OE is low, the Q outputs are in a normal logic state (high or low 

levels). 

The U74LVC563 is designed for 1.65V to 3.6V operation. Inputs can 

be driven from either 3.3V or 5V devices, so the U74LVC563 can be used 

in a mixed 3.3V/5V system environment. 

To ensure the high-impedance state during power up or power down, 

OE should be tied to VCC through a pull-up resistor; the minimum value of 

the resistor is determined by the current-sinking capability of the driver. 

FEATURES 

* Wide supply voltage range from 1.65V to 3.6V 

* Max tPD of 6.8 ns from D to Q at 3.3V 

* Max tPD of 7.6 ns from LE to Q at 3.3V 

* Up to 5.5V inputs accept voltages 

* Low power consumption, ICC = 10μA (Max.) at 3.6V 

* ±24mA output driver at 3V 

* IOFF supports partial-power-down mode operation 

规格书U74LVC563